Agenda: PCI-SIG Fall Virtual Developers Conference 2020

PCI-SIG Fall Virtual DevCon 2020 | Presentation Abstracts

PCI-SIG Presentations| Track 1:

PCIe 6.0 Electrical Update
Presenter: Mohiuddin Mazumder

In transitioning to PCIe 6.0, the raw data rate is doubled to 64 GT/s with PAM4 signaling. In PAM4 signaling, two bits are encoded by using four voltage levels and thus, the Unit Interval (UI) and Nyquist frequency remain the same as 32 GT/s NRZ signaling. Even though the fundamental frequency-dependent loss limitation is overcome with PAM4 signaling, PAM4 is extremely sensitive to noise making BER of 1e-12 impractical and Forward Error Correction (FEC) is required. To support lower latency link and a light FEC, BER must be less than 1e-06 before any FEC is applied and before any burst error happens. About 2x improvement in Tx jitter relative to 32 GT/s and significant improvement in Rx jitter and equalization along with improved channel quality and PCB loss less than 1.0 dB/inch at 16 GHz are necessary to support channel reach similar to what is supported in PCIe 5.0. The PCIe 6.0 Base Specification divides up the electrical layer into four components: Transmitter, Channel, Receiver and Reference Clock. The PCIe 6.0 specification for each component is discussed along with the rationale behind the parameters specified and the measurement methodologies. This session is geared toward an audience with knowledge of the PCIe Base Electrical specification.

PCIe CEM Previews
Presenter: Manisha Nilange
This presentation provides updates on the recent PCI Express specification development work in the PCI-SIG Electromechanical Workgroup. The presentation focuses on providing an overview of the PCI Express Card Electromechanical Specification 5.0 (CEM 5.0) updates and several improvements to the CEM connector to support 32GT/s signaling while maintaining mechanical backwards compatibility.

PCIe 6.0 PHY Logical
Presenter: Debendra Das Sharma
This session covers important aspects of PCIe 6.0 along with the rationale for these choices: the PAM-4 signaling, the Forward Error Correction, the new Cyclic Redundancy Check, the Flit Mode, new low-power state (L0p) with Flit mode, mitigations of the impact of the higher bit error on performance and reliability along with the numbers, and shared credit pool mechanism. People who are designing, validating or specifying the latest generation of PCIe components are the target audience for this session.

PCIe 6.0 Protocol Update
Presenter: Joe Cowan
This session covers PCI Express protocol developments over the last year or two, including completed ECNs, selected ECRs under development, and major protocol changes in PCIe 6.0. Completed ECNs include ATS Memory Attributes (AMA), PTM Byte Adaptation, Shadow Functions, Data Object Exchange (DOE), Component Measurement & Authentication (CMA), and Deferrable Memory Write (DMWr) with Device 3 Extended Capability. Selected ECRs under development include Integrity & Data Encryption (IDE), Combined Power, and “Can I Use”. A separate PCIe Security Updates session covers the related security ECNs and ECR in more depth. Major protocol changes for PCIe 6.0 include FLIT-Mode TLP header format. L0p replacing L0s in FLIT Mode, Shared Credit Pool, 14-Bit Tags in FLIT Mode, Deprecated features, and Strongly Recommended features becoming Mandatory.

PCIe 4.0 Compliance: Protocol Deep Dive
Presenter: Gordon Getty
This presentation discusses the requirements for PCI Express 3.x and 4.0 Protocol compliance and interoperability. It provides an in-depth review of all Protocol testing performed for the PCIe 3.x and 4.0 compliance programs—with a focus on updates/changes for the 4.0 program. Every component of PCIe Protocol compliance is discussed including Link and Transaction Layer, Retimer Logical, Lane Margining, BIOS and Configuration testing.

PCI Express Basics & Background
Presenter: Richard Solomon
In this session, attendees will learn the basics of the PCI Express Architecture. This presentation will cover the key features of PCI Express and provide an overview of the Electrical, Packet-Based Protocol and Configuration Mechanism of this high-performance serial bus architecture. This session is geared towards attendees new to PCI Express technologies.

PCI Express M.2™ Updates
Presenter: Manisha Nilange
The PCI Express M.2 Specification Revision 4.0, Version 1.0 is approaching completion and release to members. This presentation aims to provide a snapshot of the changes that have been approved in the form of ECNs post Version 1.2. In addition, part of the presentation will cover details about the M.2 Compliance Program and changes incorporated to the M.2 Specification to support PCIe 4.0.

PCIe Platform Component Security Enhancements
Presenters: Joe Cowan & Dave Harriman
As PCIe use expands to meet growing demands for more capabilities and more sensitive data processing, overall platform security faces new challenges and threats. To address these, we present security enhancements to PCIe components to raise the bar, including Component Authentication (hardware identity), Measurement (firmware identity) and Data Protection (confidentiality, integrity and anti-replay). Security is critical not only for PCIe components, but basically all platform components including other I/O, processors, DIMMs, and even power supplies and fans. Accordingly, the proposed PCIe enhancements are part of a much broader industry effort to enable fully secured platform infrastructure, with several already underway.

Members Implementation | Track 2:

Prototyping and Hardware Validation of PCIe 5.0 Designs at 32GT/s: Challenges and Solutions
Presenter: Olivier Alexandre
The number of silicon chips supporting PCIe 5.0 is already ramping up at leading edge foundries, while PCIe 4.0 only begins to hit the market with the first commercial platforms. Nonetheless, the data rate promised by the PCIe 5.0 technology is reaching a physical limit at 32GT/s speed, introducing a slew of constraints at various levels: PCB track length restriction, PCS requirements, etc. In this presentation we list and explain the challenges facing PCIe 5.0 hardware validation and prototyping, and propose ways to address these challenges.

Linux Kernel Driver for PCIe DMA Integrated IP
Presenter: Nadeem Athani
This presentation is based on providing support of Linux Kernel Driver for PCIe-DMA Integrated IP. It provides mechanism to use the existing Linux kernel DMA engine for data transfer between system memory and PCIe device. The driver is designed to be the extension of PCIe Controller in kernel. It exposes the DMA Engine APIs which are used by DMA client driver to execute DMA operation. The DMA client driver may include application specific implementation for IP. The design architecture takes into account, existing PCIe and DMA kernel framework with no additional changes and will be reference for any PCIe-DMA IP variant.

Whitebox Approach to Verify PCIe Link Training and Status State Machine
Presenter: Gaurav Brahmbhatt
Nowadays serial communication protocols like PCI Express and USB have evolved to enable high operating speeds i.e. PCIe 4.0, PCIe 5.0. This evolution has resulted in their PHY Layer protocol growing in complexity, especially the Link Training and Status State Machines' (LTSSM's) logic. A traditional test bench often concentrates on higher level functionality of LTSSM such as achieving a link up, link speed and link width updates, among other things. This paper talks about a new approach that reduces verification time and verifies the micro-level details of LTSSM functionality. Using this approach LTSSM verified thoroughly by generating random and corner case scenarios, including negative stimulus as well. We found more than 200 LTSSM RTL bugs in the DUT till now. Also, number of test cases required were reduced to around 100 as compared to 500 tests in a legacy testbench. This approach is not just limited to the LTSSM, but can be re-purposed to verify any other complex state machine.

Use Case Driven Pre-silicon PCIe Performance Analysis
Presenter: Robert Green
PCIe sub-systems in modern SoCs must be performance optimized for the various types of endpoints and software payloads they are targeted towards. A set of bare-metal benchmarks based on accelerator, NIC, and storage use-cases are presented which can be run in a pre-silicon environment to generate performance data early in the design cycle. These scenarios mimic the expected behavior of real-world software. A theoretical calculation for the effective bandwidth on the PCIe link for these software payloads can be compared to the results of the running the benchmarks and used to highlight any performance bottlenecks within the system.

PCIe 5.0 (32GT/s) Connector Compliance with Integrated Crosstalk Noise
Presenter: Steve Krooswyk
New for PCIe CEM 5.0, connectors are required to meet a minimum Integrated Crosstalk Noise (ICN) if excursions against the frequency domain limit line occur. These excursions, such as resonance, may not contribute an observable system impact. In this presentation we review connectors with resonant excursions and explain the components in the ICN calculation. Measured 5.0 connectors and measured ICN calculations are included in the presentation.

Development of a Highly Optimized PCI Express 4.0 Retimer Solution - A Case Study
Presenter: Amit Saxena
A case study of an optimized Retimer development with Mobiveil's PCI Express 4.0 Controller and Analog bits PCI Express 4.0 PHY - In this presentation we will describe the challenges of developing a low latency, high performance PCI Express 4.0 capable Retimer silicon. Retimers extend the channel reach of PCI Express beyond what is capable without it. Use cases include PCI Express channels expanding over cables, backplanes, add-in cards etc. Many high-performance applications in the data center is expected to use PCI Express 4.0 retimer silicon. In this paper we will cover design techniques to achieve better than specification defined Retimer latency, ensuring compliance and implementation of few value added features. We will also cover integration of PCIe Controller with PHY as well as verification challenges for PCI Express 4.0 Retimer and how UVM based environment helped us achieve verification closure.

Importance of Cross Combinations of Physical Layer Parameters in Verification
Presenter: Vivek Sehgal
The design verification challenges and scope keep increasing with growing complexity of PCIe based designs. This presentation describes the importance of certain Physical layer parameters like lane skew, polarity inversion, lane reversal and their verification strategy, covering the following aspects: how various cross combinations of these parameters can result in interesting verification scenarios, relevance of these scenarios in design verification, how a System Verilog UVM based constrained random verification environment can be leveraged to cover all possible scenarios, and example use cases with corresponding waveform analysis.